Si5380A-B-GM, Clock Signal Conditioner Single Ended

Technical Reference
Legislation and Compliance
RoHS Certificate of Compliance
COO (Country of Origin): TW
Product Details

Si5380 Wireless Jitter Attenuating Clock Multipliers

The Si5380 is a single chip Ultra Low Jitter, Any Frequency, 12-output JESD204B Clock Generator for 4G/LTE RRU. Integrated DSPLL technology simplifies design and PCB footprint together with removing the need for external VCXO, loop filter components and complex external filtering.

Low phase noise JESD204B clock with interated LC-VCO.

Highly immune to switching power supply noise and other noise sources.

Simple and intuitive configuration with the ClockBuilder Pro software from Silicon Labs.

Supported by the Si5380 Development Kit (RS 8807317)

- Supports JESD204B clocking: DCLK and SYSREF
- Input frequency range: 10 MHz – 750 MHz
- Output frequency range: 480 kHz – 1.47456 GHz
- Excellent jitter performance: 80 fs typ (12 kHz – 20 MHz)
- Phase noise floor: –159 dBc/Hz
- Spur performance: –103 dBc max (122.88 MHz carrier)
- Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, HCSL, and CML with programmable signal amplitude
- 4 input, 12 output, 64-pin QFN
- Temperature range: –40 to +85 °C

Specifications
Attribute Value
Number of Clock Inputs 4
Operation Mode Single Ended
Discontinued product
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