Si5347A-A-GM, Frequency Multiplier 4, 0.0001 → 712.5 MHz, 64-Pin QFN

These jitter attenuating clock multipliers combine either two or four DSPLL and provide access to any of the four inputs and provide low jitter clocks on any of the outputs.
The Silicon Labs Si5346 has two DSPLL and housed in a 44-Pin QFN package (7x7mm)
The Silicon Labs Si5347 has four DSPLL and housed in a 64-Pin QFN package (9x9mm)

- Each DSPLL generates any output frequency from any input frequency.
- Input frequency range:
- Differential: 8 kHz to 750MHz
- LVCMOS: 8 kHz to 250MHz
- Output frequency range:
- Differential: up to 712.5MHz
- LVCMOS: up to 250MHz
- Ultra low jitter - less than 100 fs typical (12kHz-20MHz)
- Configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML and HCSL with programmable signal amplitude.