Renesas Electronics 2305A-1HDCGI Clock Buffer 8-Pin SOIC
- RS Stock No.:
- 263-7872
- Mfr. Part No.:
- 2305A-1HDCGI
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal (1 tube of 97 units)*
Kr.773 575
(exc. VAT)
Kr.966 993
(inc. VAT)
FREE delivery for online orders over 500,00 kr
Temporarily out of stock
- Shipping from 12. mai 2026
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tube* |
|---|---|---|
| 97 - 194 | Kr. 7,975 | Kr. 773,58 |
| 291 - 485 | Kr. 7,76 | Kr. 752,72 |
| 582 - 970 | Kr. 7,556 | Kr. 732,93 |
| 1067 - 2425 | Kr. 7,362 | Kr. 714,11 |
| 2522 + | Kr. 7,178 | Kr. 696,27 |
*price indicative
- RS Stock No.:
- 263-7872
- Mfr. Part No.:
- 2305A-1HDCGI
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 8 | |
| Minimum Supply Voltage | -0.5V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | IDT2305A | |
| Standards/Approvals | RoHS | |
| Height | 1.5mm | |
| Length | 4.9mm | |
| Width | 3.9 mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 8 | ||
Minimum Supply Voltage -0.5V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series IDT2305A | ||
Standards/Approvals RoHS | ||
Height 1.5mm | ||
Length 4.9mm | ||
Width 3.9 mm | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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