Renesas Electronics 9DB106BGLF Clock Buffer 28-Pin TSSOP

The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.

SMBus Interface
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps