Microchip, 32-Pin VQFN-32, Ethernet Controller 10 Mbps SPI 3.3V LAN8651B1-E/LMX, Half Duplex
- RS Stock No.:
- 352-163
- Mfr. Part No.:
- LAN8651B1-E/LMX
- Brand:
- Microchip
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Kr. 49,31
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Kr. 61,64
(inc. VAT)
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Units | Per unit |
|---|---|
| 1 - 9 | Kr. 49,31 |
| 10 + | Kr. 44,39 |
*price indicative
- RS Stock No.:
- 352-163
- Mfr. Part No.:
- LAN8651B1-E/LMX
- Brand:
- Microchip
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Maximum Data Rate | 10Mbps | |
| Product Type | Ethernet Controller | |
| Communication Mode | Half Duplex | |
| Interface Type | SPI | |
| Standard Supported | IEEE | |
| Package Type | VQFN-32 | |
| Pin Count | 32 | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | IEEE Std 802.1AS, IEEE Std 1588 | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Maximum Data Rate 10Mbps | ||
Product Type Ethernet Controller | ||
Communication Mode Half Duplex | ||
Interface Type SPI | ||
Standard Supported IEEE | ||
Package Type VQFN-32 | ||
Pin Count 32 | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals IEEE Std 802.1AS, IEEE Std 1588 | ||
- COO (Country of Origin):
- TH
The Microchip MAC-PHY Ethernet Controller with SPI combines a Media Access Controller (MAC) and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface (SPI) of the LAN8650 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.
Internal wall clock
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
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