Alliance Memory AS4C64M8D3L-12BCN SDRAM 512 MB Surface, 78-Pin 8 bit FBGA-78 Ball
- RS Stock No.:
- 425-145
- Mfr. Part No.:
- AS4C64M8D3L-12BCN
- Brand:
- Alliance Memory
Subtotal (1 tray of 242 units)*
Kr. 15 049,496
(exc. VAT)
Kr. 18 811,87
(inc. VAT)
FREE delivery for online orders over 750,00 kr
Temporarily out of stock
- Shipping from 08 June 2026
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Units | Per unit | Per Tray* |
|---|---|---|
| 242 + | Kr. 62,188 | Kr. 15 049,50 |
*price indicative
- RS Stock No.:
- 425-145
- Mfr. Part No.:
- AS4C64M8D3L-12BCN
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 512MB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 800MHz | |
| Maximum Random Access Time | 20ns | |
| Mount Type | Surface | |
| Package Type | FBGA-78 Ball | |
| Pin Count | 78 | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 95°C | |
| Height | 1mm | |
| Length | 10.5mm | |
| Series | AS4C64M8D3L | |
| Standards/Approvals | RoHS, JEDEC Standard | |
| Minimum Supply Voltage | 1.283V | |
| Maximum Supply Voltage | 1.35V | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 512MB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 800MHz | ||
Maximum Random Access Time 20ns | ||
Mount Type Surface | ||
Package Type FBGA-78 Ball | ||
Pin Count 78 | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 95°C | ||
Height 1mm | ||
Length 10.5mm | ||
Series AS4C64M8D3L | ||
Standards/Approvals RoHS, JEDEC Standard | ||
Minimum Supply Voltage 1.283V | ||
Maximum Supply Voltage 1.35V | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Alliance Memory 512Mb Double-Data-Rate-3L (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Write Leveling
ZQ Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
JEDEC Standard Compliant
Related links
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