Intelligent Memory IM1G16D2DDBG-25I SDRAM 1 GB Surface, 84-Pin 16 bit FBGA-84 Ball
- RS Stock No.:
- 588-593
- Mfr. Part No.:
- IM1G16D2DDBG-25I
- Brand:
- Intelligent Memory
Subtotal (1 pack of 2 units)*
Kr.86 49
(exc. VAT)
Kr.108 112
(inc. VAT)
FREE delivery for online orders over 500,00 kr
Stock information currently inaccessible
Units | Per unit | Per Pack* |
|---|---|---|
| 2 + | Kr. 43,245 | Kr. 86,49 |
*price indicative
- RS Stock No.:
- 588-593
- Mfr. Part No.:
- IM1G16D2DDBG-25I
- Brand:
- Intelligent Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Intelligent Memory | |
| Memory Size | 1GB | |
| Product Type | SDRAM | |
| Organisation | 64M x 16 | |
| Data Bus Width | 16bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 533MHz | |
| Maximum Random Access Time | 2.5ns | |
| Mount Type | Surface | |
| Package Type | FBGA-84 Ball | |
| Pin Count | 84 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Length | 12.5mm | |
| Width | 8 mm | |
| Standards/Approvals | JEDEC, RoHS | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.9V | |
| Minimum Supply Voltage | 1.7V | |
| Select all | ||
|---|---|---|
Brand Intelligent Memory | ||
Memory Size 1GB | ||
Product Type SDRAM | ||
Organisation 64M x 16 | ||
Data Bus Width 16bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 533MHz | ||
Maximum Random Access Time 2.5ns | ||
Mount Type Surface | ||
Package Type FBGA-84 Ball | ||
Pin Count 84 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Length 12.5mm | ||
Width 8 mm | ||
Standards/Approvals JEDEC, RoHS | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.9V | ||
Minimum Supply Voltage 1.7V | ||
- COO (Country of Origin):
- TW
The Intelligent Memory Eight bank DDR DRAM is organized as 8 banks x 8Mbit x 16. It achieves high-speed data transfer rates by employing a chip architecture that prefetches multiple bits and synchronizes the output data to the system clock, ensuring efficient and reliable performance.
Power down mode
Auto refresh and self refresh
Automatic and controlled precharge command
Related links
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