Nexperia 74AUP2G08DC,125, 2 2-Input AND Schmitt Trigger Input Logic Gate, 8-Pin VSSOP

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Subtotal (1 pack of 25 units)*

Kr.61 10 

(exc. VAT)

Kr.76 375 

(inc. VAT)

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Units
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Per Pack*
25 - 225Kr. 2,444Kr. 61,10
250 - 600Kr. 2,325Kr. 58,13
625 - 1225Kr. 2,201Kr. 55,03
1250 - 2475Kr. 2,151Kr. 53,78
2500 +Kr. 2,055Kr. 51,38

*price indicative

Packaging Options:
RS Stock No.:
153-2935
Mfr. Part No.:
74AUP2G08DC,125
Brand:
Nexperia
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Brand

Nexperia

Product Type

Logic Gate

Logic Function

AND

Mount Type

Surface

Number of Elements

2

Number of Inputs per Gate

2

Schmitt Trigger Input

Yes

Package Type

VSSOP

Pin Count

8

Logic Family

AUP

Input Type

CMOS

Maximum High Level Output Current

-4mA

Minimum Operating Temperature

-40°C

Maximum Propagation Delay Time @ CL

8.3ns

Maximum Operating Temperature

125°C

Length

2.1mm

Height

0.85mm

Standards/Approvals

No

Series

74AUP2G

Width

2.4 mm

Minimum Supply Voltage

0.8V

Maximum Supply Voltage

3.6V

Maximum Low Level Output Current

4mA

Output Type

ECL

Automotive Standard

No

Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Low static power consumption, ICC = 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of VCC

IOFF circuitry provides partial power-down mode operation

Multiple package options

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