Renesas Electronics 9DB102BGILF, LVDS Buffer Dual TTL Buffer, 20-Pin TSSOP
- RS Stock No.:
- 217-7928
- Mfr. Part No.:
- 9DB102BGILF
- Brand:
- Renesas Electronics
Bulk discount available
Subtotal (1 tube of 74 units)*
Kr.2 572 536
(exc. VAT)
Kr.3 215 67
(inc. VAT)
FREE delivery for online orders over 500,00 kr
In Stock
- 74 unit(s) ready to ship
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Tube* |
|---|---|---|
| 74 - 74 | Kr. 34,764 | Kr. 2 572,54 |
| 148 - 222 | Kr. 30,243 | Kr. 2 237,98 |
| 296 - 444 | Kr. 28,577 | Kr. 2 114,70 |
| 518 - 962 | Kr. 25,725 | Kr. 1 903,65 |
| 1036 + | Kr. 24,367 | Kr. 1 803,16 |
*price indicative
- RS Stock No.:
- 217-7928
- Mfr. Part No.:
- 9DB102BGILF
- Brand:
- Renesas Electronics
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Drivers | 2 | |
| Input Type | TTL | |
| Output Type | Buffer | |
| Number of Elements per Chip | 2 | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Drivers 2 | ||
Input Type TTL | ||
Output Type Buffer | ||
Number of Elements per Chip 2 | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.
2 - 0.7 V HCSL differential output pairs
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
Related links
- Renesas Electronics 9DB102BGILF 20-Pin TSSOP
- Renesas Electronics 9DB403DGILFT 20-Pin TSSOP
- Texas Instruments CDCLVD1204RGTT LVDS 16-Pin QFN
- Renesas Electronics 9DB102BGLFT PLL Clock Buffer 20-Pin 20-pin TSSOP
- Renesas Electronics 853S014AGILF Buffer 20-Pin TSSOP
- Renesas Electronics 9DBL411BGLFT Clock Buffer 20-Pin TSSOP
- Renesas Electronics 9DBL411BGILF Clock Buffer 20-Pin TSSOP
- Renesas Electronics 9DB102BGLF Clock Buffer 20-Pin TSSOP
