Winbond DDR2 SDRAM 128 MB Surface, 84-Pin 16 bit TFBGA

RS Stock No.:: 188-2580
Mfr. Part No.:: W9712G6KB25I
Brand:: Winbond

Winbond DDR2 SDRAM 128 MB Surface, 84-Pin 16 bit TFBGA

Subtotal (1 tray of 209 units)*

Kr.4 239 356

(exc. VAT)

Kr.5 299 195

(inc. VAT)

FREE delivery for online orders over 500,00 kr

Temporarily out of stock

Shipping from 30. juni 2026

Need more? Click ‘Check delivery dates’ to find extra stock and lead times.

Units	Per unit	Per Tray*
209 +	Kr. 20,284	Kr. 4 239,36

*price indicative

RS Stock No.:: 188-2580
Mfr. Part No.:: W9712G6KB25I
Brand:: Winbond

Specifications

Technical Reference

Legislation and Compliance

Product Details

Find similar products by selecting one or more attributes.

Select all	Attribute	Value
	Brand	Winbond
	Product Type	DDR2 SDRAM
	Memory Size	128MB
	Organisation	16M x 8 Bit
	Data Bus Width	16bit
	Address Bus Width	15bit
	Number of Bits per Word	8
	Maximum Random Access Time	0.4ns
	Number of Words	16M
	Mount Type	Surface
	Package Type	TFBGA
	Minimum Operating Temperature	-40°C
	Pin Count	84
	Maximum Operating Temperature	95°C
	Width	8.1 mm
	Series	W9712G6KB
	Standards/Approvals	RoHS
	Length	12.6mm
	Height	0.8mm
	Minimum Supply Voltage	1.7V
	Maximum Supply Voltage	1.9V
	Automotive Standard	No
	Supply Current	135mA

	Select all
	Brand Winbond
	Product Type DDR2 SDRAM
	Memory Size 128MB
	Organisation 16M x 8 Bit
	Data Bus Width 16bit
	Address Bus Width 15bit
	Number of Bits per Word 8
	Maximum Random Access Time 0.4ns
	Number of Words 16M
	Mount Type Surface
	Package Type TFBGA
	Minimum Operating Temperature -40°C
	Pin Count 84
	Maximum Operating Temperature 95°C
	Width 8.1 mm
	Series W9712G6KB
	Standards/Approvals RoHS
	Length 12.6mm
	Height 0.8mm
	Minimum Supply Voltage 1.7V
	Maximum Supply Voltage 1.9V
	Automotive Standard No
	Supply Current 135mA

Datasheet W9712G6KB25I

The W9712G6KB is a 128M bits DDR2 SDRAM and speed involving -25, 25I and -3.

Double Data Rate architecture: two data transfers per clock cycle

CAS Latency: 3, 4, 5 and 6

Burst Length: 4 and 8

Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data

Edge-aligned with Read data and center-aligned with Write data

DLL aligns DQ and DQS transitions with clock

Differential clock inputs (CLK and /CLK)

Data masks (DM) for write data

Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS

Posted /CAS programmable additive latency supported to make command and data bus efficiency

Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality

Auto-precharge operation for read and write bursts

Auto Refresh and Self Refresh modes

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18

Winbond DDR2 SDRAM 128 MB Surface, 84-Pin 16 bit TFBGA

FREE delivery for online orders over 500,00 kr

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