Toshiba 74HC74D 2 Flip Flop IC 74HC, CMOS, 14-Pin SOIC
- RS Stock No.:
- 171-3146P
- Mfr. Part No.:
- 74HC74D
- Brand:
- Toshiba
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Subtotal 100 units (supplied on a continuous strip)*
Kr. 426,20
(exc. VAT)
Kr. 532,80
(inc. VAT)
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Units | Per unit |
|---|---|
| 100 - 480 | Kr. 4,262 |
| 500 - 980 | Kr. 3,775 |
| 1000 + | Kr. 3,409 |
*price indicative
- RS Stock No.:
- 171-3146P
- Mfr. Part No.:
- 74HC74D
- Brand:
- Toshiba
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74HC | |
| Product Type | Flip Flop IC | |
| Output Type | CMOS | |
| Clock Frequency | 29MHz | |
| Polarity | Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SOIC | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 32ns | |
| Flip-Flop Type | D Flip-Flop | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 85°C | |
| Number of Elements per Chip | 2 | |
| Standards/Approvals | No | |
| Series | 74HC74D | |
| Length | 8.95mm | |
| Height | 1.38mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74HC | ||
Product Type Flip Flop IC | ||
Output Type CMOS | ||
Clock Frequency 29MHz | ||
Polarity Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SOIC | ||
Pin Count 14 | ||
Maximum Supply Voltage 6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 32ns | ||
Flip-Flop Type D Flip-Flop | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 85°C | ||
Number of Elements per Chip 2 | ||
Standards/Approvals No | ||
Series 74HC74D | ||
Length 8.95mm | ||
Height 1.38mm | ||
Automotive Standard No | ||
The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of theCLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: fMAX = 77 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V
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