Alliance Memory AS4C64M8D3-12BIN SDRAM 512 MB Surface, 78-Pin 8 bit FBGA
- RS Stock No.:
- 665-382
- Mfr. Part No.:
- AS4C64M8D3-12BIN
- Brand:
- Alliance Memory
Unavailable
RS will no longer stock this product.
- RS Stock No.:
- 665-382
- Mfr. Part No.:
- AS4C64M8D3-12BIN
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 512MB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 8 | |
| Maximum Clock Frequency | 800MHz | |
| Number of Words | 64 | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Pin Count | 78 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 95°C | |
| Standards/Approvals | RoHS, JEDEC | |
| Length | 10.5mm | |
| Height | 1mm | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.425V | |
| Maximum Supply Voltage | 1.575V | |
| Select all | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 512MB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Number of Bits per Word 8 | ||
Maximum Clock Frequency 800MHz | ||
Number of Words 64 | ||
Mount Type Surface | ||
Package Type FBGA | ||
Pin Count 78 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 95°C | ||
Standards/Approvals RoHS, JEDEC | ||
Length 10.5mm | ||
Height 1mm | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.425V | ||
Maximum Supply Voltage 1.575V | ||
- COO (Country of Origin):
- TW
The Alliance Memory 512Mb DDR3 DRAM in a 78-ball FBGA package features a double data rate architecture for high-speed operation and is internally configured as an eight-bank DRAM. It is organized as 8Mbit x8 I/Os x8 banks and supports double-data-rate transfer rates of up to 1600Mb/sec per pin, making it ideal for general-purpose applications. The device complies with all key DDR3 DRAM specifications, with control and address inputs synchronized using a pair of externally supplied differential clocks.
8 internal banks for concurrent operation
8n-bit prefect architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Burst type is Sequential and Interleave
Output Driver Impedance Control
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